1. Field of the Invention
The present invention relates to an insulated gate semiconductor device for controlling a large power, in particular to a semiconductor device which is called "a power MOS device" and a method of manufacturing the same. Representatively, there are a power MOS FET (hereinafter referred to simply as "power MOS") which is an MOS gate device, an IGBT (insulated gate bipolar transistor), etc.
2. Description of the Related Art
In recent years, the semiconductor devices have been tended to be made more fine so that the machining dimensions of a deep sub-micron region are required. However, there has been known that, in the MOS FET, when a channel formation region is identical in dimension with the deep sub-micron region, there arises a problem such as the phenomenon of a short channel effect.
The short channel effect is the phenomenon developed because the charges in the channel formation region are largely influenced by not only a gate voltage but also the charges in a depletion layer of a source/drain region, an electric field and a potential distribution as the line width of a gate electrode is shortened, that is, a channel formation region is shortened. There has been known that the short channel effect leads to a variety of problems such as the lowering of a threshold value voltage, the deterioration of a sub-threshold characteristic, the deterioration of a withstand voltage, and so on.
The problem of the above phenomenon is common to all of the device having an MOS structure that operates with the formation of a channel. This is also seen in the power MOS device for controlling a large power without exception. There are many cases in which the power MOS device requires a high withstand voltage because there are used a large current and a large voltage, and therefore the deterioration of a withstand voltage caused by the short channel effect leads to a large problem.
In general, the power MOS device is directed to a semiconductor device which is used as a switching device of an electronic equipment, or the like, and the power devices of a high-speed MOS such as a power MOS or an IGBT have been known as examples. These semiconductor devices are characterized in that they are different in structure from an IC or an LSI because a large voltage and a large current are used.
A basic structure of a single cell of the power MOS is shown in FIG. 2. In the figure, marks represented by "+" or "-" are used as an index representing the relative strength of conductivity. In other words, for example, n.sup.+ represents n-type stronger than n.sup.-.
In FIG. 2, a weak n-type (n.sup.-) region 202 that is called "a drift region" is formed on a semiconductor substrate 201 having an n.sup.+ -type through an epitaxial growth. The semiconductor substrate 201 having the n.sup.+ -type functions as a drain region as it is.
Also, a strong p-type (p.sup.+) region 203 is formed on the drift region 203 through an impurity diffusion, and a source region 204 having the n.sup.+ -type is also disposed therein. A part of the strong p-type (p.sup.+) region 203, which is located immediately under a gate electrode, functions as a channel formation region. Then, it is structured such that a gate electrode 206 is disposed on a semiconductor surface through a gate insulating film 205.
In case of the power MOS structure of this type, when a positive voltage is applied to the gate electrode 206, a channel region 207 is formed in the p-type region (channel formation region) 203 in the vicinity of the gate electrode 206 so that a current flows in a direction indicated by an arrow (in case of the enhancement n-channel FET).
In this way, the MOS IC used for an IC or an LSI is structured such that a current flows laterally in the vicinity of the surface of the semiconductor substrate, whereas the power MOS shown in FIG. 2 is characterized in that source/drain regions are disposed so as to sandwich the semiconductor substrate therebetween so that a current flows vertically.
The reason why the power MOS is structured such that a current flows vertically as described above is that an on-state resistance (a resistant value of all the regions in which a drain current flows) is reduced to increase a current density. This is one of important structures for the power MOS which allows a large current to flow therein and performs a high-speed operation.
Hence, in the case where a high-speed operation characteristic is required, it is desirable that a resistivity of the drift region is small, but on the contrary, in the case where a high withstand voltage characteristic is required, it is devised that the resistivity of the drift region is made large to improve the withstand voltage.
However, in the case where the high-speed operation characteristic is required, when the resistivity of the drift region is made small, there may arise such a problem that the device is destroyed because the withstand voltage exceeds a limit when the withstand voltage is deteriorated by the short channel effect.
A state where the short channel effect is developed in the power MOS is simplified and shown in FIG. 3. FIG. 3 represents an enlarged diagram of the periphery of the channel region 207 shown in FIG. 2.
In FIG. 3, reference numeral 301 denotes a drift region formed of a weak n-type (n.sup.-); 302 is a channel formation region formed of a strong p-type (p.sup.+); 303 is a source region formed of a strong n-type (n.sup.+); 304 is a channel region; and 305 is a gate electrode. Also, a dotted line indicated by reference numeral 306 represents a depletion layer formed when the drain voltage is small.
Normally, a current that flows in the channel region 304 is controlled by only the gate voltage. In this case, as indicated by reference numeral 306, the depletion layer in the vicinity of the channel region 304 is disposed substantially in parallel with the channel to form a uniform electric field.
However, as the drain voltage becomes high, the depletion layer in the vicinity of the drift region 301 extends toward the channel region 304 and the source region 303 so that, as represented by a solid line 307, the charges or the electric field of the drain depletion layer adversely affect the depletion layer in the vicinity of the source region 303 and the channel region 304. In other words, an on-state current is varied by the complicated distribution of the electric field, thereby leading to a circumstance where it is difficult to control the current which flows in the source region 303 and the channel region 304 by only the gate voltage.
An energy state of the periphery of the channel formation region in the case where the short channel effect is developed will be described with reference to FIG. 4. In FIG. 4, respective illustrations of states indicated by solid lines show an energy band in the vicinity of the source region 401, the p-type region (channel formation region) 402 and the drift region 403 when the drain voltage is 0 V.
In that state, when a sufficiently large drain voltage Vd is applied, the states indicated by the solid lines are changed into states indicated by dotted lines in FIG. 4. In other words, the charges and the electric field in the depletion layer of the drift region which are formed by the drain voltage Vd adversely affect the charges in the depletion layers of the source and channel formation regions 401 and 402, with the result that the energy (potential) state changes continuously from the source region 401 to the drift region 403.
Then, as an influence of the short channel effect on the semiconductor device, there occurs the lowering of the threshold value voltage (Vth) and the punch-through phenomenon. Also, when an influence of the gate voltage on the drain current is lowered by the punch-through phenomenon, the sub-threshold characteristic is deteriorated.
First, the lowering of the threshold value voltage is a phenomenon that occurs in the n-channel FET as well as the p-channel FET. Also, the degree of the lowering depends not only on the drain voltage, but also on a variety of parameters such as the concentration of the impurities in the substrate, the depth of the source/drain diffusion layers, the thickness of the gate oxide film, the substrate bias, and so on.
Although the lowering of the threshold value voltage is desirable from the viewpoint that it makes the power consumption small, it generally leads to a problem that the frequency characteristic does not become high because the drive voltage of the integrated circuit becomes small.
For that reason, up to now, it is general that as means for controlling the threshold value voltage, impurity elements that give one conductivity are uniformly added to the whole channel formation region, and the threshold value voltage is controlled with the amount of the impurity elements as added. However, even this method cannot prevent the short channel effect per se, whereby the punch-through phenomenon and so on are caused to occur. Also, since the impurities as added scatter the carriers, they cause the mobility of the carriers to be lowered.
Also, the deterioration of the sub-threshold characteristic which is caused by the punch-through phenomenon means that the sub-threshold coefficient (S-value) increases, that is, the switching characteristic of the FET is deteriorated. An influence of the short-channel effect on the sub-threshold characteristic is shown in FIG. 5.
FIG. 5 is a graph whose horizontal axis represents the gate voltage Vg, and whose vertical axis represents the logarithm of the drain current Id, and the inverse number of a slope (the sub-threshold characteristic) in the region 501 is the S-value. In FIG. 5, changes of the characteristics when the channel length is gradually shortened are compared, and the channel length is shortened toward a direction indicated by an arrow.
As a result, the slope of the characteristic becomes small as the channel length is shortened. In other words, it can be confirmed that there is a tendency that the S-value is increased. This means that the switching characteristic of the semiconductor device is more deteriorated as the channel length is shortened.
As described above, the phenomenon of the short channel effect is a serious problem even in the power MOS device, and a problem to be solved for making the semiconductor device fine in the future.
In particular, in the power MOS device, the high-speed operation characteristic and the high-withstand voltage characteristic have a relation of a trade-off, and in the case where an importance is given to the high-speed operation characteristic, the deterioration of the withstand voltage which is caused by the short channel effect is remarkable as a problem of the destruction of device.